1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection device and particularly to an ESD protection device with improved performance.
2. Description of the Prior Art
An NMOSFET is a very effective ESD protection device. In one application, with the gate connected to a gate-driving signal, the NMOSFET is used as the pull down device of a CMOS buffer to drive an output voltage. In a second application, with the gate electrically connected to the ground, the NMOSFET is used to protect an input pin or power bus during an ESD event.
In a PS mode ESD event, with a positive ESD transient voltage applied to an IC pin while a VSS power pin is at ground potential, the protection of an NMOSFET heavily depends on the snap-back mechanism for conducting large ESD current between the drain and source. At the beginning, the high electric field at the drain junction causes impact ionization, which generates both minority and majority carriers. The minority carriers flow toward the drain contact and the majority carriers flow toward the substrate/p-well contact, causing a local potential buildup in the current path in p-well. When the local substrate potential is 0.6V higher than the adjacent n+ source potential, the source junction becomes forward biased. The forward biased source junction injects minority carriers (electrons) into the p-well, and those carriers eventually reach the drain junction to further enhance the impact ionization. As a continuous loop, the MOSFET gets into a low impedance (snapback) state to conduct large ESD current.
In a multi-finger NMOS structure as shown in FIGS. 1A and 1B, not all gate fingers may turn on during an ESD event. This is because the first few gate finger having turned on quickly get into a snap-back low-impedance condition. The drain terminal to source terminal voltage is reduced to a transient voltage lower than the trigger voltage of the NMOS device. This potentially prevents other gate fingers from turning on. Therefore, with only a partial number of gate fingers turned on to absorb the ESD energy, the size of the NMOSFET is effectively reduced and the ESD protection degrades.
When a gate finger is triggered in an ESD event, the entire finger turns on. This is due to a cascading effect in which a local source junction in a forward biasing state injects numerous carriers into the substrate to flow toward the drain junction, which in turn generates more minority carriers (due to impact ionization) back toward the p+ guard ring to raise the adjacent p-well potential. Thus, the gate finger turns on into a snap back condition.
Experimental data has shown that long-gate-finger NMOS structure (e.g, 100 um×2 fingers) as shown in FIG. 2 has better PS-mode ESD protection than a short-gate-finger structure (e.g, 20 um×10 fingers) as shown in FIG. 1A, despite both structures having the same total gate width of 200 um. This is because, during a PS-mode ESD event, the many short-finger NMOSFET may have only a few fingers turned on while each finger is only 10% of the total gate width.
Prior art MOSFET-based I/O (Input/Output) structures with self-ESD protection typically include a number of NMOSFET and PMOSFET transistors. As shown in FIGS. 3A, 3B and 3C, the pull-down NMOSFET may comprise a number of gate elements, with some connected to a first gate signal for the output transistor portion, and some connected to the VSS bus/Ground as the input protection ESD structure. Similarly, the pull-up PMOSFET may comprise a number of gate elements, with some connected to a second gate signal for the output transistor portion, and some connected to the VDD bus as the input protection ESD structure. In the prior-art methods, a gate element formed of a poly-silicon element is typically coupled to either a gate signal or a power bus.